1. Technical Field
The present invention relates to a method and structure for forming an electronic package with an interconnect structure that comprises lead-free solders.
2. Related Art
A chip carrier is typically coupled to a circuit card by a solder interconnect structure that includes a grid array such as a ball grid array (BGA) or a column grid array (CGA). In particular, a lead-comprising solder interconnect (e.g., a lead-comprising solder ball of a BGA or a lead-comprising solder column of a CGA) is joined to the chip carrier by use of a first lead-comprising joining solder. Similarly, the lead-comprising solder interconnect is joined to the circuit card by use of a second lead-comprising joining solder. Unfortunately, lead is toxic and environmentally hazardous. Thus, there is a need for a lead-free solder interconnect structure for coupling a chip carrier to a circuit card.
The present invention provides electronic structure comprising:
an electronic component; and
a solder structure solderably coupled to the electronic component, wherein the solder structure includes:
a joiner interconnect comprising a joiner solder, wherein the joiner solder is lead free; and
a core interconnect comprising a core solder, wherein the core solder is lead free, wherein the joiner interconnect solderably couples an end of the core interconnect to the electronic component, and wherein a liquidus temperature of the joiner solder is less than a solidus temperature of the core solder.
The present invention provides an electronic structure, comprising:
a first electronic component;
a second electronic component; and
a solder interconnect structure which solderably couples the first electronic component to the second electronic component, wherein the solder interconnect structure includes:
a first joiner interconnect comprising a first joiner solder that is lead free and has a liquidus temperature T1L;
a second joiner interconnect comprising a second joiner solder that is lead free and has a liquidus temperature T2L; and
a core interconnect comprising a core solder that is lead free and has a solidus temperature TCS, wherein the first joiner interconnect solderably couples a first end of the core interconnect to the first electronic component, wherein the second joiner interconnect solderably couples a second end of the core interconnect to the second electronic component, wherein T1L less than TCS, and wherein T2L less than TCS.
The present invention provides a method of forming an electronic structure, comprising:
providing an electronic component, a joiner solder, and a core interconnect, wherein the joiner solder is lead free, wherein the core interconnect includes a core solder, wherein the core solder is lead free, and wherein a liquidus temperature T1L of the joiner solder is less than a solidus temperature TCS of the core solder;
soldering an end of the core interconnect to the electronic component with the joiner solder, including reflowing the joiner solder at a reflow temperature that is above T1L and below TCS; and
cooling the joiner solder to a temperature that is below a solidus temperature of the joiner solder.
The present invention provides a method of forming an electronic structure, comprising:
providing a module that includes a first electronic component, a first joiner interconnect, and a core interconnect, wherein the first joiner interconnect solderably couples a first end of the core interconnect to the first electronic component, wherein the first joiner interconnect includes a first joiner solder that is lead free and has a liquidus temperature T1L, wherein the core interconnect comprises a core solder that is lead free and has a solidus temperature TCS, and wherein T1L less than TCS;
providing a second electronic component and a second joiner solder, wherein the second joiner solder is lead free and has a liquidus temperature T2L, and wherein T2L less than TCS;
soldering a second end of the core interconnect to the second electronic component with the second joiner solder, including reflowing the second joiner solder at a reflow temperature TR2 that is above T2L and below TCS; and
cooling the second joiner solder to a temperature that is below a solidus temperature of the second joiner solder.
The present invention provides a lead-free solder interconnect structure for coupling a chip carrier to a circuit card.